Gating signals with SSA

Table III shows the average area and power overheads ($A_{oh}$ and $P_{oh}$) for the extra gating circuitry as a percentage of the respective area and power of the AO, IUPO and IAPO circuits. The corresponding gated circuits are called AO-gated, IUPO-gated and IAPO-gated, respectively. Such small overheads are almost negligible compared to the large power savings achieved.

Table III: Gating signals with SSA.

	$A_{oh}$	$P_{oh}$	$P_i$	$P_d$	$P_{tot}$
	$\%$	$\%$	$\%$	$\%$	$\%$
AO-gated	0.1	2.6	49.4	11.8	16.9
IUPO-gated	0.04	3.5	23.4	9.5	9.9
IAPO-gated	0.03	4.8	15.7	4.8	5.1

The table also shows the average power reduction in interconnects ($P_{i}$), DPUs ($P_{d}$) and the total circuit ($P_{tot}$) when signal gating is applied to AO, IUPO and IAPO circuits (thus generating AO-gated, IUPO-gated and IAPO-gated circuits, respectively). Even for IAPO circuits, the net total power reduction is 5.1% ( the power overhead is included in this number) at a negligible area overhead. For AO and IUPO circuits, the power reductions are more because they have more SSA in both interconnects and DPUs. It is worth noting that due to the difficulty in estimating glitches at the RTL, glitching power is not taken into consideration. If it could be estimated, we expect the power reduction to be much more.