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Introduction
High-level synthesis for low power has
attracted significant
attention [1,2,3,4,5,6,7,8,9,10,11].
It takes as its input a behavioral description in the form of a
control-data flow graph (CDFG) and outputs a power-optimized RTL
circuit. Most previous work tried to minimize power consumed by
datapath units while ignoring that by interconnects. As shown
in [12], interconnects consume a significant
fraction of total circuit power. Moreover, since wire delay is
becoming more significant, wire buffer insertion has become
popular [13]. This in turn has increased the portion
of circuit power consumed by interconnects.
High-level synthesis can target either bus-based or
multiplexer-based interconnections among datapath
units [14]. It has a significant impact on the
switching activity and topology of the interconnects in the
resultant design. To optimize interconnects during high-level
synthesis is therefore important.
Interconnect cost has been considered in high-level synthesis by
many
researchers [19,20,21,22,23,24,25].
In most cases, the number of interconnects/multiplexers is used as
the interconnect cost. None of these works use physical
information to estimate interconnect cost accurately. Moreover,
all these works are targeted at only bus-based architectures and
only area/performance optimization.
For bus-based RTL architectures and system-on-chip (SOC) designs,
bus coding has been proposed to reduce switching
activity [15,16,17].
The work in [18] proposes to optimize bus power by
appropriately binding data transfers to busses. These techniques,
however, do not take wire length into consideration, and are not
applicable to multiplexer-based interconnects.
Taking physical level information into account during high-level
synthesis has also attracted a lot of
attention [26,27,28,29,30,31,32,33,34,35].
Earlier work used floorplanning information in high-level
synthesis to improve design area or performance estimation. Only
some recent works took interconnect power consumption into
consideration [2,33].
In [33], the switching activity on CDFG edges was
profiled. It was used with the floorplanner to optimize the power
consumption of inter-module data transfers. Only the floorplanner
was made interconnect power-aware. Moreover, the coupling effect
between wires was not taken into consideration.
In [2], the authors preserved the locality and
regularity in input behaviors to optimize bus power consumption in
bus-based architectures, though they did not distinguish between
busses with different switching activities. Due to the mapping of
behavioral identities (operations and variables) to physical
identities (functional units and registers), locality and
regularity in the behavior does not necessarily guarantee locality
in the physical design .
In this work, we provide a comprehensive treatment of
interconnect-aware high-level synthesis for low power targeting
multiplexer-based interconnects.
We evaluate the power consumption in the steering logic and clock
distribution network as well as data transfer wires, using early
floorplanning information. Since coupling capacitances are
expected to dominate the wire capacitance in future technologies,
we take coupling into account while estimating wire power
consumption. Moreover, we propose metrics to guide the binding
process to preserve and create locality in the physical
implementation. Unlike [2], our methodology does
not assume behaviorial locality and regularity. While
concentrating on the interconnect power issue, our synthesis flow
and methodology maximize the orthogonality to other problems as
scheduling, floorplanning, wire and RTL power modeling
It is well-known that there can be significant spurious switching
activity (SSA), , activity not required by the behavioral
specification, in datapath units [36,37,38].
We found that there is significant SSA in interconnects too. It
increases the power consumption in the interconnects as well as
other circuit components. We propose techniques to suppress it.
The paper is organized as follows. We offer our observations and
motivational examples in Section II, and discuss RTL
interconnect power estimation in Section III. We
present methodologies for interconnect-aware binding in Section
IV, and address the problem of interconnect SSA in
Section V. After giving the framework of our
interconnect-aware high-level synthesis system in Section
VI, we provide experimental results and conclude in
Sections VII and VIII, respectively.
Next: Observations and Motivational Examples
Up: Interconnect-aware Low Power High-level
Previous: Interconnect-aware Low Power High-level
Lin Zhong
2003-10-11